1. Field of the Invention
The present invention relates to a clock synchronous semiconductor device, and particularly to a clock synchronous semiconductor device, such as a clock synchronous semiconductor memory device, of which clock access time can be reduced. More particularly, the invention relates to a structure of a data output portion of a clock synchronous semiconductor memory device.
2. Description of the Background Art
FIG. 31 schematically shows a structure of a data output portion of a clock synchronous semiconductor memory device in the prior art. In FIG. 31, a clock synchronous semiconductor memory device includes an internal power supply circuit VDC for producing an internal power supply voltage Vint by lowering an external power supply voltage Vex supplied to a power supply node PDE, a memory cell array MA having a plurality of memory cells arranged in rows and columns, a read circuit PAM receiving internal power supply voltage Vint from internal power supply circuit VDC as one operation power supply voltage, for amplifying data of a selected memory cell in memory cell array MA, a clock buffer CB receiving internal power supply voltage Vint as one operation power supply voltage, for buffering an externally applied clock signal CLKe to produce an internal clock signal CLKi, and an output data control circuit ODC for transferring memory cell data read from read circuit PAM onto an internal data bus DBB in synchronization with clock signal CLKi and transmitting the read data to a data output node group QG.
Output data control circuit ODC receives internal power supply voltage Vint supplied from internal power supply circuit VDC, an external power supply voltage Vex supplied from power supply node PDE and an output power supply voltage VDDQ supplied to a power supply node PDD. Output power supply voltage VDDQ is independent of external power supply voltage Vex, and is dedicated to the output buffer. The purpose of supplying external power supply voltage Vex to output data control circuit ODC is to convert an internal read signal, which is at the level of internal power supply voltage Vint and is applied onto internal data bus DBB, into a signal at the level of external power supply voltage Vex for outputting the read data at the level of output power supply voltage VDDQ to data output node group QG. Now, an operation of a clock synchronous semiconductor memory device shown in FIG. 31 will be briefly described below with reference to a timing chart of FIG. 32.
In a clock cycle #a, a read command instructing data reading is issued. In accordance with this read command, selection of an addressed memory cell column in memory cell array MA and activation of read circuit PAM are performed under the control of a command control circuit (not shown). When read circuit PAM is activated, the data of the selected memory cell is transmitted onto internal data bus DBB. Output data control circuit ODC is in a latch state when internal clock signal CLKi is at L-level so that data read onto data bus DBB is not transferred in clock cycle #a.
In a clock cycle #b, output data control circuit ODC takes in data on internal data bus DBB and then transfers the data to data output node group QG in synchronization with internal clock signal CLKi.
Data Q read onto data output node group QC is sampled by an external device in synchronization with external clock signal CLKe in a clock cycle #c. Accordingly, the read data is sampled by the external device when two clock cycles elapse after the read command is applied. Clock cycle periods required after application of the read command and before output of valid data is referred to as a "CAS latency" or a "column latency".
As shown in FIG. 32, the data can be transferred to an external device in synchronization with clock signal CLKi. Since the data transfer speed is determined by clock signal CLKi (CLKe), data transfer can be performed in synchronization with a fast clock signal, and therefore fast data transfer can be achieved.
Internal power supply circuit VDC is used for reducing a charge/discharge current of a signal line and therefore a whole power consumption of the semiconductor memory device. With increase in memory capacity, MOS transistors which are the components of the memory device are increasingly miniaturized. For ensuring reliability of miniaturized MOS transistors (insulated gate field effect transistors), the power supply voltage applied to the MOS transistors is lowered. The reliability of the MOS transistor to be ensured specifically includes reliability (breakdown characteristics) of a gate insulating film having a thickness reduced in accordance with miniaturization of the element, and reliability of an immunity to hot carriers caused by a short-channelization of the MOS transistors due to miniaturization of the components (if hot carries generated by a high drain electric field are trapped in a gate insulating film, insulating properties of the gate insulating film will deteriorate).
FIG. 33 shows an example of a structure of an output data control circuit in the prior art. FIG. 33 shows a structure of a circuit for transferring data of one bit.
In FIG. 33, output data control circuit ODC includes a clocked gate 900 activated when internal clock signal CLKi is at H-level, to pass signals on an internal data line pair DB and /DB, an output data latch circuit 902 for latching signals applied from clocked gate 900 onto internal read data lines /RL4 and RL4, an inverter circuit 903 inverting a signal applied from output data latch circuit 902 onto internal read data line RL5, and cascaded inverter circuits 904 and 905 of two stages receiving a signal applied from output data latch circuit 902 onto a complementary internal read data line /RL5. Each of these clocked gate 900, output data latch circuit 902, and inverter circuits 903, 904 and 905 receives internal power supply voltage Vint as one operation power supply voltage.
Clocked gate 900 includes an NAND circuit G1 receiving internal clock signal CLKi and a signal on internal data line DB, and an NAND circuit G2 receiving internal clock signal CLKi and a signal on internal data line /DB. Internal data lines DB and /DB are included in internal data bus DBB shown in FIG. 31, and receives complementary data signals from read circuit PAM.
Output data latch circuit 902 includes NAND circuits G3 and G4 forming a flip-flop set when the signal on internal read data line /RL4 is at L-level and reset when the signal on internal read data line RL4 is at L-level. Output data latch circuit 902 further includes NAND circuits G5 and G6 forming a flip-flop reset when the signal on internal read data line /RL4 is at L-level and set when the signal on internal read data line RL4 is at L-level. Output data latch circuit 902 inverts the signals that are transferred from clocked gate 900 onto internal read data lines /RL4 and RL4, and latches and transfers the inverted signals onto internal read data lines RL5 and /RL5.
Output data control circuit ODC further includes a level converting circuit 906 for converting an amplitude of the signal on internal read data line RL5 to a level of external power supply voltage Vex in accordance with the signal on internal read data line RL5 and the output signal of inverter circuit 903, and an output buffer 908 for driving a data output node Q in accordance with the signal that is applied from level converting circuit 906 onto an internal read data line /RL3P and the signal that is applied from inverter circuit 905 onto an internal read data line /RL3N.
Level converting circuit 906 includes a P-channel MOS transistor T1 connected between an external power supply node and a node N1 and having a gate connected to a node N2, a P-channel MOS transistor T2 connected between the external power supply node and node N2 and having a gate connected to node N1, an N-channel MOS transistor T3 connected between node N1 and a ground node supplying a ground voltage providing a reference voltage with a gate thereof connected to internal read data line RL5, an N-channel MOS transistor T4 connected between node N2 and the ground node and having a gate receiving the output signal of inverter circuit 903, a P-channel MOS transistor T5 turned on when the signal on node N2 is at L-level, to drive an internal read data line /RL3P to the level of external power supply voltage Vex, and an N-channel MOS transistor T6 turned on when the signal on node N2 is at H-level, to drive internal read data line /RL3P to the level of ground voltage VSS.
In this level converting circuit 906, when the signal on internal read data line RL5 is at H-level, MOS transistor T3 is on and MOS transistor T4 is off, so that node N2 is charged to the level of external power supply voltage Vex by MOS transistor T2. MOS transistors T5 and T6 form a CMOS inverter, and the signal on internal read data line /RL3 attains the L-level equal to the reference voltage level.
When the signal on internal read data line RL5 is at L-level, MOS transistor T3 is off, and MOS transistor T4 is on so that node N2 is discharged to the level of ground voltage. Responsively, transistor T5 is turned on so that the signal on internal read data line /RL3P attains H-level of external power supply voltage Vex.
Output buffer 908 includes a P-channel MOS transistor MP connected between the power supply node and the output node and having a gate connected to internal read data line /RL3P, and an N-channel MOS transistor MN connected between data output node Q and the ground node supplying reference potential VSSQ with a gate thereof coupled to internal read data line /RL3N. Data output node Q has a relatively large load, and MOS transistors MP and MN have increased sizes (ratio of gate width to gate length) for rapidly driving the relatively large load. For rapid driving of relatively large gate capacitances of MOS transistors MP and MN, level converting circuit 906 utilizes the CMOS inverter formed of MOS transistors T5 and T6, and inverter 905 is also employed.
In the structure of output data control circuit ODC shown in FIG. 33, when internal clock signal CLKi is at H-level, clocked gate 900 is turned on, and signals corresponding to the signals on internal data lines DB and /DB are transferred onto internal read data lines RL5 and /RL5, and are latched. When internal clock signal CLKi is at L-level, clocked gate 900 is off, and the signals on internal read data lines RL4 and /RL4 are at H-level, and output data latch 902 is in the latching state. Accordingly, clocked gate 900 and output data latch 902 transfer the data on internal data lines DB and /DB in synchronization with rising of internal clock signal CLKi. Level converting circuit 906 is provided for reliably turning off MOS transistor MP included in output buffer 908. Therefore, external power supply voltage Vex is at a voltage level equal to or higher than output power supply voltage VDDQ.
FIG. 34A shows another structure of the output data control circuit in the prior art. In the structure of output data control circuit ODC shown in FIG. 34A, output data latch circuit 902 generates signals at L-level onto internal read data lines RL5 and /RL5 when an output enable control signal ZOEM is inactive. When output enable control signal ZOEM is in the active state of L-level, output data latch circuit 902 operates as a latch circuit to latch signals that are applied from clocked gate 900 onto internal read data lines /RL4 and RL4. Structures other than the above are the same as those shown in FIG. 33, and the corresponding portions bear the same reference numerals.
Output data latch circuit 902 shown in FIG. 34A includes NOR gates G9 and G10 receiving output enable control signal ZOEM, an NAND circuit G4 receiving the signal on internal read data line RL4 and the output signal of NOR gate G9, an AND circuit G7 receiving the signal on internal read data line /RL4 and the output signal of NAND circuit G4, an NAND circuit G5 receiving the signal on internal read data line /RL4 and the output signal of NOR circuit G10, and an AND circuit G8 receiving the signal on internal read data line RL4 and the output signal of NAND circuit G5.
When output enable control signal ZOEM is in the inactive state of H-level, the output signals of NOR circuits G9 and G10 attain L-level so that the signal potentials on internal read data lines RL5 and /RL5 attain L-level. In this state, the signal transmitted from inverter circuit 905 on internal read data line /RL3N is at L-level, and the signal transmitted from level converting circuit 906 on internal read data line /RL3P attains H-level of external power supply voltage Vex. Accordingly, both MOS transistors MP and MN of output buffer 908 are off, and output buffer 908 enters the output high-impedance state.
When output enable control signal ZOEM attains the active state of L-level, NOR circuits G9 and G10 operate as inverter circuits. In this state, AND circuit G7 and NOR circuit G9 operate, in combination, as an NAND circuit, and AND circuit G8 and NOR circuit G10 operate, in combination, as an NAND circuit. In this state, therefore, the signals on internal read data lines /RL4 and RL4 are latched, and the signals corresponding to the data latched on internal read data lines RL5 and /RL5 are generated as is done by the structure of the output data latch circuit already described and shown in FIG. 33.
Output enable control signal ZOEM is driven to the active state at an elapse of the CAS latency less one cycle from application of a read command. Output enable control signal ZOEM is kept active for a clock cycle period of a burst length equal to the number of data successively read after application of the read command. FIG. 34B shows a case where the burst length is equal to four.
Output data Q is transmitted via clocked gate 900 in accordance with internal clock signal CLKi. Therefore, valid data is output in synchronization with rising of internal clock signal CLKi after elapsing of a delay time of the output data control circuit.
In the structure of output data control circuit ODC shown in FIG. 34A, the internal circuit operation can be stopped by utilizing output enable control signal ZOEM, and the current consumption can be reduced. In the case where data output node Q is common to a terminal for write data inputting, output buffer 908 can enters the output high-impedance state by utilizing output enable control signal ZOEM, and the write data can be internally written without data conflict.
FIG. 35A shows still another structure of output data control circuit ODC in the prior art. Output data control circuit ODC shown in FIG. 35A differs from the structure of the output data control circuit shown in FIG. 34A in that output data latch circuit 902 is supplied with an output enable signal ZOE instead of output enable control signal ZOEM, and that level conversion is effected on both the complementary data signals of output data latch circuit 902. Structures other than the above are the same. The corresponding portions bear the same reference numerals, and their description is not repeated.
In the output data control circuit ODC shown in FIG. 35A, output enable signal ZOE is applied, instead of output enable control signal ZOEM, to NOR circuits G9 and G10 of output data latch circuit 902.
Level converting circuit 910 includes a level converting circuit 906 for generating a signal at the level of external power supply voltage Vex onto internal read data line /RL3P in accordance with the signal on internal read data line RL5 and the output signal of inverter circuit 903, and a level converting circuit 912 for transmitting a signal at the level of external power supply voltage Vex onto internal read data line /RL3N in accordance with the signal on internal read data line /RL5 and an output signal of an inverter circuit 911 inverting the signal on internal read data line /RL5. Level converting circuit 906 provided for internal read data line RL5 and inverter circuit 903 has the same structure as level converting circuit 906 shown in FIG. 34, and the corresponding portions bear the same reference numerals.
Level converting circuit 912 has a P-channel MOS transistor T7 connected between the external power supply node and a node N3 and having a gate connected to internal read data line /RL3N, a P-channel MOS transistor T8 connected between the external power supply node and internal read data line /RL3N and having a gate connected to node N3, an N-channel MOS transistor T9 connected between node N3 and the ground node and having a gate connected to internal read data line /RL5, and an N-channel MOS transistor T10 connected between internal read data line /RL3N and the ground node and having a gate receiving the output signal of inverter circuit 911. Level converting circuit 912 transmits the signal at the level of external power supply voltage Vex onto internal read data line /RL3N when the signal on internal read data line /RL5 is at H-level.
Output enable signal ZOE becomes active before valid data is output after application of a read command as shown in FIG. 35B. Output enable signal ZOE is periodically driven to the active state of L-level while the burst length data are being outputted. Output enable signal ZOE is deactivated to attain H-level in each cycle, and internal read data lines RL5 and /RL5 are once precharged to L-level. Responsively, internal read data lines /RL3P and /RL3N are set to H-level and L-level (ground voltage level), respectively, and output buffer circuit 908 is set to the output high-impedance state.
In FIG. 35B, output enable signal ZOE is driven to the inactive state of H-level for a predetermined period in synchronization with rising of internal clock signal CLKi. However, output enable signal ZOE may be driven to H-level for a predetermined period before completion of each clock cycle as shown by dotted line in FIG. 35B.
By temporarily setting output buffer circuit 908 to the output high-impedance state, fast change in voltage on output node Q can be achieved in the data read operation.
As shown in FIGS. 34A and 35A, the output data control circuit performs the data output operation using internal clock signal CLKi as a trigger signal for reading. Therefore, data is transferred to data output node Q in synchronization with the clock signal, and fast data transfer is achieved.
Owing to the operation of lowering external power supply voltage Vex to produce internal power supply voltage Vint by internal power supply circuit VDC, the signal amplitude of an internal signal line can be reduced, and the charge/discharge current and therefore the current consumption can be reduced. In the case where the components are formed of MOS transistors, however, the operation speed changes in accordance with the gate voltage. In the case where internal power supply voltage Vint is utilized as the operation power supply voltage, therefore, the operation speed of the MOS transistor lowers, and the transmission speed of the internal signal lowers.
In the case where clock buffer CB produces internal clock signal CLKi from external clock signal CLKe as shown in FIG. 36, internal clock signal CLKi is transmitted from clock buffer CB to output data control circuit ODC with a delay time of td0. Accordingly, start of the operation of clocked gate 900 is delayed with respect to external clock signal CLKe. Further, internal clock signal CLKi has an amplitude of the internal power supply voltage level, and the operation speed of clocked gate 900 also lowers (the components of clocked gates 900 are MOS transistors), so that the output of the clocked gate likewise changes with a certain delay time of td1. This output signals of clocked gate 900 are applied to the output data latch. Output data latch circuit 902 likewise operates using internal power supply voltage Vint as one operation power supply voltage, and the operation speed thereof is slow. The output signal of output data latch circuit 902 likewise changes with a delay time of td2 with respect to the output of clocked gate 900. Particularly, if output data latch circuit 902 is supplied with output enable control signal ZOEM or output enable signal ZOE, these output control signals affect the delay time of the output signals of output data latch circuit 902 because these output control signals ZOEM and ZOE are signals each having an amplitude of the internal power supply voltage level.
An output signal of output data latch circuit 902 is converted into the signal at the level of external power supply voltage Vex by level converting circuit 906 or 910, for outputting. The level converting circuit produces a signal at the level of external power supply voltage Vex. The converted signal has a large logical amplitude as compared with an output signal of a usual logic gate, and therefore has a delay time longer than a signal of an amplitude of the internal power supply voltage level. Accordingly, the delay time in level converting circuit 906 is longer than the delay time in other logic circuit, and the output signal of level converting circuit 906 is made definite after a delay time of td3. Output buffer circuit 908 drives output node Q in accordance with the output signal of level converting circuit 906 or 910, and an innegligible gate delay time td4 is likewise present in output buffer 908. Accordingly, valid data is applied to node Q with a delay of a time (td0+td1+td2+td3+td4) with respect to external clock signal CLKe.
Meanwhile, in a fast semiconductor memory device, it is important to reduce an access time tAC after a trigger signal for externally outputting read data is externally applied and before the read data is actually and externally outputted. In a signal waveform diagram of FIG. 36, an external device samples the output data of this semiconductor memory device in synchronization with a rising edge of external clock signal CLKe. Relative to this rising of external clock signal CLKe, read data Q is required to have a setup time tsu. For stable data sampling, it is preferable to maximize the setup time tsu. Accordingly, clock access time tAC must be minimized for increasing the setup time tsu. This is particularly required when external clock signal CLKe is fast and has a shortened period.
In many cases, output power supply voltage VDDQ applied to the output buffer is at a voltage level equal to or slightly lower than external power supply voltage Vex, but is higher than internal power supply voltage Vint. As described above, the voltage higher than the internal power supply voltage is employed as output power supply voltage VDDQ to be applied to the output buffer. This is because a load present on the data output node must be driven fast, and because a data signal of an amplitude corresponding to the power supply voltage of an external device must be transferred (external power supply voltage Vex is the system power supply voltage).
If external clock signal CLKe is made faster, its period T becomes short. In shortening the period T of external clock signal CLKe, the clock speed can be increased only to a restricted extent due to clock access time tAC so that the semiconductor memory device cannot be applied to a system operating in accordance with a fast clock.
In the case where many circuits related to clock access time tAC operate using internal power supply voltage Vint as the operation power supply voltage, such operations are required, during a period in which the semiconductor memory device receives the external clock signal and outputs data via the output buffer, that data signals and control signals are transferred via circuits using internal power supply voltage Vint as the operation power supply voltage and then the data signals are converted in voltage level to external power supply voltage Vex level or the output power supply voltage VDDQ level and then the data is outputted via the output buffer. In any of the circuits, the signal propagation time is long, and therefore clock access time tAC becomes long, so that it is impossible to implement a semiconductor memory device capable of fast data output.
In the case where the level conversion is performed within an output data control circuit, a difference in propagation time between complementary data signals and therefore error data may outputted if only one of the complementary data signals is subject to level conversion. In the structure shown in FIG. 35A, the numbers of gates for level conversion of the complementary data signals are different from each other, resulting in a similar problem.
This semiconductor memory device is merely required to perform data output in synchronization with the clock signal, and the same or similar problem occurs in any one of a SDRAM (Synchronous Dynamic Random Access Memory), a synchronous SRAM (Static Random Access Memory) and serial EEPROM (Electrically Erasable and Programmable Nonvolatile Semiconductor Memory Device).
In addition, the semiconductor device such as a processor operates in synchronization with a clock signal, and outputs/inputs data and signals in synchronization with the clock signal, and may be suffered from the similar problem.